1. Field
Exemplary embodiments of the present invention relate to an internal voltage generating circuit, and more particularly, to the circuit of reduced voltage setting time and power consumption.
2. Description of the Related Art
Various types of semiconductor devices use various internal voltages having different levels from levels of external voltages supplied from the outside. For example, a memory device uses core voltage VCORE used in a core region, reference voltage VREF used in a buffer, and the like.
A common scheme for generating the internal voltages is voltage division.
FIG. 1 is a configuration diagram of an internal voltage generating circuit as prior art.
Referring to FIG. 1, the internal voltage generating circuit includes a resistor string 110 including a plurality of series resistors connected between a power supply voltage terminal VDD and a ground voltage terminal VSS and a voltage selection circuit 120. The voltage selection circuit 120 selects voltage as internal voltage VREF of one from the plurality of nodes of the resistor string 110 in response to voltage selection information SEL_INFO. The internal voltage generating circuit determines a level of the internal voltage VREF depending on the selected node of the plurality of series resistor.
There is tradeoff relationship between a current consumed in the circuit and voltage setting time for each node of the resistor string 110 to reach targeted voltage from the start of operation of the internal voltage generating circuit. When resistances of resistors of the resistor string 110 are large, that is, all the resistances of the resistor string 110 is large, current consumed by the internal voltage generating circuit is reduced. However, the voltage setting time is required much. On the other hand, when the resistances of resistors of the resistor string 110 are small, current consumed by the circuit is increased. However, in this case, there is advantageous in that the voltage setting time is short.
According to recent needs for a memory device, the reference voltage VREF generated in the memory device needs to have a voltage level determined by a code in one of two or more preset ranges (A and B and C and D) with the preset voltage setting time.